Fission-track constraints on the thermal and tectonic evolution of the Apuseni Mountains (Romania)

New zircon and apatite fission-track (FT) data, including apatite thermal modelling, are combined with an extensive literature survey and reconnaissance-type structural fieldwork in the Eastern Apuseni Mountains. This leads to a better understanding of the complex structural and thermal history of a key area at the boundary between two megatectonic units in the Balkan peninsula, namely the Tisza and Dacia Mega-Units. Following Late Jurassic obduction of the Transylvanian ophiolites onto a part of the Dacia Mega-Unit, that is, the Biharia nappe system, both units were buried to a minimum of 8km during late Early Cretaceous times when these units were underthrust below the Tisza Mega-Unit consisting of the present-day Codru and Bihor nappe systems. Tisza formed the upper plate during Early Cretaceous (‘Austrian') east-facing orogeny. Turonian to Campanian zircon FT cooling ages (95-71Ma) from the Bihor and Codru nappe systems and the Biharia and Baia de Arieş nappes (at present the structurally lowest part of the Dacia Mega-Unit) record exhumation that immediately followed a second Cretaceous-age (i.e. Turonian) orogenic event. Thrusting during this overprinting event was NW-facing and led to the overall geometry of the present-day nappe stack in the Apuseni Mountains. Zircon FT ages, combined with thermal modelling of the apatite FT data, show relatively rapid post-tectonic cooling induced by a third shortening pulse during the latest Cretaceous (‘Laramian' phase), followed by slower cooling across the 120°-60°C temperature interval during latest Cretaceous to earliest Paleogene times (75-60Ma). Cenozoic-age slow cooling (60-40Ma) was probably related to erosional denudation postdating ‘Laramian' large-scale updomin

Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

Abstract A low-power digital charge balancing system, which ensures the safe operation of constant-current biphasic stimulation is presented. The concept of the proposed charge-balancing technique is to utilize a hybrid method consisting of anodic pulse modulation and short-term offset current injection. Furthermore, a dual thresholding strategy is employed to guarantee precise and low-power imbalance compensation. The charge-balancing system is capable of canceling large persistent imbalances by adjusting the input code of an 8-bit current-steering digital-to-analog converter (DAC) as well as injecting an offset current in a power-efficient way. The performance of the designed charge balancer is evaluated by modeling a 1 mA biphasic constant-current stimulator with 8-bit DAC resolution. The charge-balancing system is implemented on a Cyclone IV FPGA, and measurement results evidence the safe, accurate and low-power charge-balancing performance in which the balance offset current injection is performed in less than 5% of the stimulation time while the dynamic power consumption is at 0.76 mW Materials VHDL codes are provided suitable for ASIC and FPGA implementation of the proposed charge balancing processor. How to use The first step is to read the manuscript to extract essential design parameters such as clock frequency, target hardware, ADC specifications, etc. Then, a project file should be created in Quartus. the top-level vhdl file is (top_level_CB_final). All aother vhdl files must be included to the top level file

Input-output measures for model reduction and closed-loop control: Application to global modes

International audienceFeedback control applications for flows with a large number of degrees of freedom require the reduction of the full flow model to a system with significantly fewer degrees of freedom. This model-reduction process is accomplished by Galerkin projections using a reduction basis composed of modal structures that ideally preserve the input-output behaviour between actuators and sensors and ultimately result in a stabilized compensated system. In this study, global modes are critically assessed as to their suitability as a reduction basis, and the globally unstable, two-dimensional flow over an open cavity is used as a test case. Four criteria are introduced to select from the global spectrum the modes that are included in the reduction basis. Based on these criteria, four reduced-order models are tested by computing open-loop (transfer function) and closed-loop (stability) characteristics. Even though weak global instabilities can be suppressed, the concept of reduced-order compensators based on global modes does not demonstrate sufficient robustness to be recommended as a suitable choice for model reduction in feedback control applications. The investigation also reveals a compelling link between frequency-restricted input-output measures of open-loop behaviour and closed-loop performance, which suggests the departure from mathematically motivated H-measures for model reduction toward more physically based norms; a particular frequency-restricted input-output measure is proposed in this study which more accurately predicts the closed-loop behaviour of the reduced-order model and yields a stable compensated system with a markedly reduced number of degrees of freedom. © 2011 Cambridge University Press

Why may reduced order models based on global modes not work for closed loop control?

National audienceIn this article, we use a reduced model based on global modes to stabilize a globally unstable cavity flow. We show that although the full-state control is successful, the partial state controller cannot stabilize the perturbations. We introduce the notion of full-state measurement control to analyze this failure and show that it is due to a lack of information of the reduced model about the stable subspace. In particular, the input-output behavior is identified as the key parameter to be captured by the reduced model. A criterion is then derived in order to select the stable global modes which are likely to contribute to the input-output behavior. These critical modes are found to be impossible to compute because of the non-normality of the Navier-Stokes operator, which leads us to the conclusion that global modes are not suitable for control based reduced models

Closed-loop control of an open cavity flow using reduced-order models

International audienceThe control of separated fluid flow by reduced-order models is studied using the two-dimensional incompressible flow over an open square cavity at Reynolds numbers where instabilities are present. Actuation and measurement locations are taken on the upstream and downstream edge of the cavity. A bi-orthogonal projection is introduced to arrive at reduced-order models for the compensated problem. Global modes, proper orthogonal decomposition (POD) modes and balanced modes are used as expansion bases for the model reduction. The open-loop behaviour of the full and the reduced systems is analysed by comparing the respective transfer functions. This analysis shows that global modes are inadequate to sufficiently represent the inputoutput behaviour whereas POD and balanced modes are capable of properly approximating the exact transfer function. Balanced modes are far more efficient in this process, but POD modes show superior robustness. The performance of the closed-loop system corroborates this finding: while reduced-order models based on POD are able to render the compensated system stable, balanced modes accomplish the same with far fewer degrees of freedom. © 2009 Cambridge University Press

Spreading vectors for similarity search

Discretizing multi-dimensional data distributions is a fundamental step of modern indexing methods. State-of-the-art techniques learn parameters of quantizers on training data for optimal performance, thus adapting quantizers to the data. In this work, we propose to reverse this paradigm and adapt the data to the quantizer: we train a neural net which last layer forms a fixed parameter-free quantizer, such as pre-defined points of a hyper-sphere. As a proxy objective, we design and train a neural network that favors uniformity in the spherical latent space, while preserving the neighborhood structure after the mapping. We propose a new regularizer derived from the Kozachenko--Leonenko differential entropy estimator to enforce uniformity and combine it with a locality-aware triplet loss. Experiments show that our end-to-end approach outperforms most learned quantization methods, and is competitive with the state of the art on widely adopted benchmarks. Furthermore, we show that training without the quantization step results in almost no difference in accuracy, but yields a generic catalyzer that can be applied with any subsequent quantizer.Comment: Published at ICLR 201

Comportamento térmico de um refrigerador doméstico quando submetido a abertura e fechamento de porta

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia Mecânica.À medida em que os aspectos relacionados à eficiência energética e usabilidade dos refrigeradores tornam-se requisitos ambientais e mercadológicos de suma importância, o conhecimento detalhado dos mecanismos de transferência de calor e massa que governam o desempenho térmico do produto se torna condição necessária para o atendimento das exigências normativas e de mercado. Neste sentido o presente trabalho tem por objetivo o estudo e a modelação do comportamento térmico de um refrigerador sujeito à abertura e fechamento de porta, de forma a possibilitar a quantificação do incremento de energia sensível e latente associada a este evento, bem como disponibilizar uma metodologia de análise de engenharia para uso no projeto de refrigeradores. O modelo matemático desenvolvido foi implementado computacionalmente e o sistema de equações foi resolvido com a aplicação do método de Newton-Raphson marchando-se no tempo para obtenção da resposta transiente das variáveis termodinâmicas associadas ao problema. Experimentos foram realizados para validar o modelo matemático proposto e quando confrontados os resultados numéricos e experimentais apresentaram boa concordânci

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and faulttolerance into these devices. Moreover, fault tolerant properties of multi- layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 µm CMOS technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6μs, at full load transition. The total ground current including the bandgap reference circuit is 28μA and the active chip area measures 290μm×360μm in a 0.18μm CMOS technolog